A semiconductor device, such as a memory device or a data latch circuit, has a storage node consisting of a combination of two inverters. If high-energy particle beams, such as energetic radiations or ions, strike a conventional inverter in operation, the energetic particles are likely to leave behind electron-hole pairs in elements of the inverter, or generate electric charges, as a result of their actions on the elements, such as ionization and excitation. The generated electric charges may cause the so-called “single-event transient phenomenon” that they flow in various regions of the inverter according to electric fields in the elements, and the occurrence of such phenomenon leads to malfunctions of the elements, for example, transiently flipping or inverting an output of the inverter. The phenomenon occurring in an inverter constituting a memory device is likely to cause a serious malfunction or inversion of stored information. This effect is referred to as “single event effect (SEE) (in this case, single event upset (SEU))”. SEE is often observed in environments with a high possibility of the presence of high-energy particles, such as high altitude, cosmic space and radiation-related facilities, and regarded as one factor obstructive to a normal operation of a computer under such environments. While it is contemplated to fully shield the high-energy particles in a physical or mechanical manner so as to prevent SEE, such an approach is not realistic. As practical and effective measures against SEE, it is necessary to develop an inverter or memory device with a structure tolerant to SEE by itself.
FIG. 1 is a circuit diagram showing a conventional inverter 1I1. As used in this specification, reference codes are defined as follows:                D: input data signal;        G: input clock signal;        Gi: clock signal (in-phased relative to the input clock signal G);        GBi: inverted clock signal;        Q: output data signal;        XQ: inverted output data signal;        VDD: source voltage from first voltage source; and        VSS: source voltage [0 (zero) V] from second voltage source.        
The inverter 1I1 comprises a p-channel MOS transistor 1P1 and a n-channel MOS transistor 1N1, which are connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source (VDD) to a node connected to the side of a second voltage source (VSS). When SEE occurs, either one of the transistors which is in an OFF state, for example, the p-channel MOS transistor 1P1 which is receiving a clock signal G having a high level, is momentarily changed from the OFF state to an ON state, so that an inverted clock signal GBi which is being output at a low level is momentarily shifted to a high level.
FIG. 2 is a circuit diagram showing a data latch circuit 1 using a conventional inverter. In order to produce an inverted clock signal GBi to be input into the data latch circuit 1, the inverter 111 illustrated in FIG. 1 is used in combination therewith. In the data latch circuit 1, when a clock signal G has a low level, an output data signal Q is generated at the same logic level as that of an input data signal D (transparent mode or through mode). At a rise timing of the clock signal G, an input data signal D is received from a clocked inverter 1I2 in an input stage, and latched. The latched data will be held during a period where the clock signal G has a high level (latch mode). Specifically, the latched data is held by a storage node consisting of a clocked inverter 1I3 and an inverter 1I4 which are cross-connected between respective outputs and inputs thereof. An output data signal Q and an inverted output data signal XQ are output, respectively, from an inverter 1I5 and an inverter 1I6 which serve as a buffer circuit. As one example, given that, during the latch mode, either one of the clocked inverter 1I3 and the inverter 1I4 which serve as a storage node is changed from an OFF state to an ON state due to SEE. In this case, an output of the affected inverter including transistors is shifted to an opposite logic level, and this change in logic value is input into the other inverter to invert its output. Consequently, a logic value in the storage node is inverted, resulting in occurrence of SEE. As another example, given that either one of a transistor 1P3 and a transistor 1N3 of the clocked inverter 1I2 in the input stage, each of which is set in an OFF state during the latch mode to prevent any input data signal D from being transmitted to subsequent stages, is changed to an ON state due to SEE. In this case, an input data signal D will be output to the subsequent stages (in an inverted state). Then, if the input data signal D has a logic level opposite to a logic state stored on the storage node, stored data will be inverted (the SEU occurs). As above, the conventional inverter and the conventional memory device including such an inverter are extremely susceptible to SEE.
A conventional element for a fundamental logic circuit is also susceptible to SEE. FIG. 9 is a circuit diagram showing a conventional 2-input NAND element, and FIG. 10 is a circuit diagram showing a conventional 3-input NAND element. FIG. 11 is a circuit diagram showing a conventional 2-input NOR element, and FIG. 12 is a circuit diagram showing a conventional 3-input NOR element. In each circuit of these elements, if a transistor in an OFF state is changed to an ON state due to SEE, an output of the transistor is likely to be largely changed to the opposite logic level. Thus, in an element receiving an output from the malfunctioning element, a logic value of the input can be inverted (single event transient (SET) as one cause of SEE occurs).
Heretofore, there has been known the following inverter and memory device with a structure tolerant to the above SEE [a technique disclosed in Japanese Patent Application No. 2002-200130 (JP 2004-048170 A1)]. FIG. 3 is a circuit diagram showing an inverter 2I with a redundant or double structure. Specifically, in the inverter 2I, a first p-channel MOS transistor 2P1 and a first n-channel MOS transistor 2N1 are connected in series with respect to a source or drain line in this order in a direction from a node connected to the side of a first voltage source to a node connected to the side of a second voltage source. Further, a second p-channel MOS transistor 2P2 and a second n-channel MOS transistor 2N2 are connected, respectively, to the first p-channel MOS transistor 2P1 and the first n-channel MOS transistor 2N1 through respective gates thereof, and connected in series with respect to the source or drain line, to form a double structure.
Based on the following operation, the above inverter 2I can suppress SEE to some extent. When a clock signal G has a high level, each of the transistors 2P1, 2P2 is in an OFF state, and each of the transistors 2N1, 2N2 is in an ON state. Further, an inverted clock signal GBi, or output, has a low level. Given that either one of the transistors 2P1, 2P2 in the OFF state is changed to an ON state due to SEE caused by incident high-energy particles. In this case, the remaining one of the other transistors 2P1, 2P2 connected in series with respect to the source or drain is maintained in the OFF state. Thus, a change in output level due to SEE is blocked by the transistor in the OFF state, and an output or an inverted clock signal GBi is free of the influence thereof. In this way, even if either one of the transistors has malfunction as described above, the inverter will be less subject to SEE in its entirely. This inverter can be used to form a memory device or data latch circuit having some level of SEE tolerance.